In recent years, along with the progress of a semiconductor device with a higher integration degree and a higher density, a semiconductor device with a built-in inductance passive element, which was connected externally as a separate element in an earlier device, has become commercially practical. Such a highly integrated semiconductor device is required to satisfy mutually contradictory conditions so as to prevent the superposing of noise and an unnecessary signal on an electrical signal of a circuit and to allow for the arrangement of input/output wirings and terminals for a large number of circuit blocks that are highly integrated.
Referring to FIGS. 6 to 8, a configuration of a conventional semiconductor device with a built-in spiral inductor will be described below. FIG. 6 is a plan view, FIG. 7 is a cross-sectional view taken along line C–C′ of FIG. 6 and FIG. 8 is a cross-sectional view taken along line D–D′ of FIG. 6.
In FIG. 6, reference numeral 1 denotes a spiral inductor, around which connection terminals 2a, 2b and 2c leading to a printed board or the like are disposed. The spiral inductor 1 is connected with a circuit block 7 by way of a wiring 5 and a via 6 that is for the interlayer connection of the wiring layer. As shown in FIG. 7, the wiring 5 and the via 6 are formed at a multilayered wiring region 3 including a wiring layer and an insulation layer that are provided on a semiconductor substrate 4. As shown in FIG. 8, the spiral inductor 1 and the connection terminals 2a, 2b and 2c (FIG. 8 illustrates the connection terminal 2a only) are disposed on an upper surface of the multilayered wiring region 3.
As countermeasures against digital noise in such a configuration, a known configuration, for example, is such that electromagnetic shielding is provided so as to surround a spiral inductor 1, the shielding being formed across the entire multilayered region including a layer constituting the spiral inductor 1 (See JP 2003-68862 A, FIG. 1, for example).
In the configuration like the conventional example, however, in the case where any one of the connection terminals 2a to 2c functions as an input/output terminal through which an electrical signal passes or a connection terminal with high impedance, the spiral inductor is affected by noise and an unnecessary signal.
Furthermore, in order to eliminate the noise and the unnecessary signal, all of the connection terminals should have low impedance such as a ground level as shown by the connection terminal 2C. This imposes a considerable restriction on a layout configuration of the semiconductor device, which results in an increase in size of the semiconductor device.
Furthermore, in the case of the configuration described in JP 2003-68862 A, the size of the block constituting the spiral inductor becomes large because the entire multilayered wiring region is shielded around the spiral inductor. Additionally, this configuration imposes a restriction on a low-impedance wiring such as the ground also, so that the flexibility of wiring layout, which is an advantage of the multilayered wiring structure, is impaired, thus resulting in an increase in size of the semiconductor device.